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? freescale semiconductor, inc., 2009. all rights reserved. 64-lqfp case 840f 80-lqfp case 917a ? 8-bit hcs08 central processor unit (cpu) ? up to 40 mhz cpu at 3.6 v to 2.1 v across temperature range of ?40 c to 85 c ? up to 20 mhz at 2.1 v to 1.8 v across temperature range of ?40 c to 85 c ? hc08 instruction set with added bgnd instruction ? support for up to 32 interrupt/reset sources ?on-chip memory ? dual array flash read/progr am/erase over full operating voltage and temperature ? random-access memory (ram) ? security circuitry to prevent un authorized access to ram and flash contents ? power-saving modes ? two low-power stop modes ? reduced-power wait mode ? low-power run and wait modes allow peripherals to run while voltage regulator is in standby ? peripheral clock gating register can disable clocks to unused modules, thereby reducing currents ? very low-power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to time-of-day (tod) module ?6 s typical wakeup time from stop3 mode ? clock source options ? oscillator (xosc) ? loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz ? internal clock source (ics) ? internal clock source module containing a frequency-lock ed-loop (fll) controlled by internal or external reference; precision trimming of internal reference allows 0.2% reso lution and 2% deviation over temperature and voltage; supporting bus frequencies from 1 mhz to 20 mhz ? system protection ? watchdog computer operating properly (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage warning with interrupt ? low-voltage detection with reset or interrupt ? illegal opcode detection with re set; illegal address detection with reset ? flash block protection ? development support ? single-wire bac kground debug interface ? breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) ? on-chip in-circuit emulator (ice) debug module containing three comparators and nine trigger modes ? peripherals ? lcd ? up to 8 36 or 4 40 lcd driver with internal charge pump and option to provide an internally-regulated lcd reference that can be trim med for contrast control ? adc ?10-channel, 12-bit resolution; up to 2.5 s conversion time; automatic compare function; temperature sensor; operation in stop3; fully functional from 3.6 v to 1.8 v ? iic ? inter-integrated circuit bus module to operate at up to 100 kbps with maximum bus loadi ng; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; broadcas t mode; 10-bit addressing ? acmp ? analog comparator wi th selectable interrupt on rising, falling, or ei ther edge of comparator output; compare option to fixed internal refe rence voltage; outputs can be optionally routed to tpm module; operation in stop3 ? scix ? two full-duplex non-return to zero (nrz) modules (sci1 and sci2); lin master extended break generation; lin slave extended break detec tion; wakeup on active edge ? spi ? full-duplex or single-wire bidirectional; double-buffered transmit and rece ive; master or slave mode; msb-first or lsb-first shifting ? tpmx ? two 2-channel (tpm1 and tpm2); selectable input capture, output compare, or bu ffered edge- or center-aligned pwm on each channel ? tod ? (time-of-day) 8-bit, quarter second counter with match register; external clock source for precise time base, time-of-day, calendar, or task scheduling functions ? vrefx ? trimmable via an 8-bit register in 0.5 mv steps; automatically loaded with room temperature value upon reset; can be enabled to operate in st op3 mode; trim re gister is not available in stop modes. ? input/output ? dedicated accurate voltage re ference output pin, 1.2 v output (vrefox); trimmable with 0.5 mv resolution ? up to 39 gpios, two output-only pins ? hysteresis and configurable pu llup device on all input pins; configurable slew rate and dr ive strength on all output pins ? package options ? 14mm 14mm 80-pin lqfp, 10 mm 10 mm 64-pin lqfp freescale semiconductor data sheet: technical data an energy efficient solution by freescale document number: mc9s08ll64 rev. 4, 08/2009 mc9s08ll64 series covers: mc9s08ll64 and MC9S08LL36
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 2 contents revision history to provide the most up-to-date information, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to ve rify you have the latest information available, refer to: http://freescale.com/ the following revision history table summariz es changes contained in this document. related documentation find the most current versi ons of all documents at: http://www.freescale.com rev date description of changes 1 7/2008 intial release of the electrical characteristics in the reference manual. 2 01/2009 initial release after product redefinition and restructuring of information into a separate data sheet and reference manual. 3 03/2009 incorporated revisions for customer release. 4 08/2009 completed all the tbds. corrected pin out in the figure 2 , figure 3 and ta b l e 2 . updated v oh , |i in |, |i oz |, r pu , r pd , added |i int | in the ta b l e 8 . updated ta b l e 9 . updated errefsten and added lcd in the ta b l e 1 0 . updated f adack , e tue , dnl, inl, e zs and e fs in the ta bl e 1 8 . updated v room temp in the ta bl e 1 9 . reference manual ? mc9s08ll64rm contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, cpu, and all module information. 1 devices in the mc9s08ll64 series. . . . . . . . . . . . . . . . . . . . . 3 2 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 parameter classification. . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 9 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 esd protection and latch-up immunity . . . . . . . . . . . . 11 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 supply current characteristics. . . . . . . . . . . . . . . . . . . 23 3.8 external oscillator (xoscvlp) characteristics . . . . . . 24 3.9 internal clock source (ics) characteristics . . . . . . . . . 26 3.10 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.10.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.10.2 tpm module timing. . . . . . . . . . . . . . . . . . . . . .29 3.10.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.11 analog comparator (acmp) electricals . . . . . . . . . . . .33 3.12 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.13 vref specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.14 lcd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.15 flash specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.16 emc performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3.16.1 radiated emissions . . . . . . . . . . . . . . . . . . . . . .40 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1 device numbering system . . . . . . . . . . . . . . . . . . . . . .41 4.2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.3 mechanical drawings . . . . . . . . . . . . . . . . . . . . . . . . . .41
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 3 1 devices in the mc9s08ll64 series table 1 summarizes the feature set availabl e in the mc9s08ll64 series of mcus. table 1. mc9s08ll64 series features by mcu and package the block diagram in figure 1 shows the structure of the mc9s08ll64 series mcu. feature mc9s08ll64 MC9S08LL36 package 80-pin lqfp 64-pin lqfp 64-pin lqfp flash 64 kb (32,768 and 32,768 arrays) 36 kb (24,576 and 12,288 arrays) ram 4000 4000 acmp yes yes adc 10-ch 8-ch 8-ch iic yes yes irq yes yes kbi 8 8 sci1 yes yes sci2 yes yes spi yes yes tpm1 2-ch 2-ch tpm2 2-ch ? ? tod yes yes lcd 8 36 4 40 8 24 4 28 8 24 4 28 vrefo1 yes no no vrefo2 no yes yes i/o pins 1 1 the 39 i/o pins include two output-only pins and 18 lcd gpio. 39 37 37
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 4 figure 1. mc9s08ll64 series block diagram ? ? v refh ? ? 12-bit pins are not available on 64-pin packages. lcd[8:12] and lcd[31:37] are not available on the 64-pin package. v refh and v refl are internally connected to v dda and v ssa for the 64-pin package. vrefo2 is available only on the 64-pin package. when ptb2 is configured as reset , the pin becomes bi-directional with output being an open-drain drive. when ptc6 is configured as bkgd, the pin becomes bi-directional. 8-bit keyboard interrupt ( kbi ) iic module ( iic ) serial peripheral interface ( spi ) user flash b user ram on-chip ice debug module ( dbg ) (ll64 = 32,768 bytes) hcs08 core cpu bkgd int bkp 2-channel timer/pwm ( tpm1 ) hcs08 system control resets and interrupts modes of operation power management cop irq lvd low-power oscillator internal clock source ( ics ) serial communications 2-channel timer/pwm ( tpm2 ) v ss v dd voltage regulator user flash a (ll36 = 24,576 bytes) ptc7/irq/tclk ptc5/tpm2ch1 ptc4/tpm2ch0 port b ptb5/mosi/scl ptb4/miso/sda ptb2/reset ptb1/xtal ptb0/extal pta7/kbip7/adp11/acmp? pta6/kbip6/adp10/acmp+ pta4/kbip4/adp8/lcd43 interface ( sci1 ) ptb7/txd2/ss ptb6/rxd2/spsck txd1 rxd1 ss spsck scl sda mosi miso v ssa v dda xtal extal irq kbi[7:0] port a reset tpm2ch0 analog-to-digital converter ( adc ) analog comparator ( acmp ) acmp+ acmp? time of day module ( tod ) tpm2ch1 tclk tpm1ch0 tpm1ch1 tclk pta3/kbip3/scl/mosi/adp7 pta2/kbip2/sda/miso/adp6 pta1/kbip1/spsck/adp5 pta0/kbip0/ss /adp4 port c port d port e ptd[7:0]/lcd[7:0] pte[7:0]/lcd[13:20] ptc6/acmpo//bkgd/ms (ll64 = 32,768 bytes) (ll36 = 12,288 bytes) 4 kb pta5/kbip5/adp9/lcd42 acmpo bkgd/ms serial communications interface ( sci2 ) txd2 rxd2 ptc3/tpm1ch1 ptc1/txd1 ptc0/rxd1 ptc2/tpm1ch0 v ll1 v lcd (lcd) v ll2 v ll3 v cap1 v cap2 liquid crystal display v refl adp[11:4] lcd[43:0] vref2 vref1 notes ? ? ? ? ? vrefo2 vrefo1 ? ? ? adp0 adp12 adp0 adp12
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 5 2 pin assignments this section shows the pin assignments for the this section shows the pin assignments for the mc9s08ll64 series devices. figure 2. 64-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64-pin lqfp pte2/lcd15 pte3/lcd16 pte4/lcd17 pte5/lcd18 pte6/lcd19 pte7/lcd20 lcd21 lcd22 lcd23 lcd24 lcd25 lcd26 lcd27 lcd28 lcd29 lcd30 pte1/lcd14 pte0/lcd13 ptd7/lcd7 ptd6/lcd6 ptd5/lcd5 ptd4/lcd4 ptd3/lcd3 ptd2/lcd2 ptd1/lcd1 ptd0/lcd0 v cap1 v cap2 v ll1 v ll2 v ll3 v lcd pta6/kbip6/adp10/acmp+ pta7/kbip7/adp11/acmp? v ssa /v refl v dda /v refh ptb0/extal ptb1/xtal v dd v ss ptb2/reset vrefo2 ptb4/miso/sda ptb5/mosi/scl ptb6/rxd2/spsck ptb7/txd2/ss ptc0/rxd1 ptc1/txd1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 lcd38 lcd39 lcd40 lcd41 pta5/kbip5/adp9/lcd42 pta4/kbip4/adp8/lcd43 pta3/kbip3/scl/mosi/adp7 pta2/kbip2/sda/miso/adp6 pta1/kbip1/spsck/adp5 pta0/kbip0/ss /adp4 ptc7/irq/tclk ptc6/acmpo/bkgd/ms ptc5/tpm2ch1 ptc4/tpm2ch0 ptc3/tpm1ch1 ptc2/tpm1ch0
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 6 figure 3. 80-pin lqfp table 2. pin availability by package pin-count <-- lowest priority --> highest 80 64 port pin alt 1 alt 2 alt3 alt4 1 2 pte0 lcd13 2 lcd12 3 lcd11 4 lcd10 5lcd9 6lcd8 7 3 ptd7 lcd7 8 4 ptd6 lcd6 adp12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80-pin lqfp pte1/lcd14 lcd35 pte0/lcd13 lcd36 lcd12 lcd37 lcd10 lcd38 lcd9 lcd39 lcd8 lcd40 ptd3/lcd3 lcd41 ptd2/lcd2 ptd1/lcd1 ptd0/lcd0 pta5/kbip5/adp9/lcd42 v cap1 pta4/kbip4/adp8/lcd43 v cap2 pta3/kbip3/scl/mosi/adp7 v ll1 pta2/kbip2/sda/miso/adp6 v ll2 pta1/kbip1/spsck/adp5 ptd7/lcd7 pta0/kbip0/ss /adp4 ptd6/lcd6 pte2/lcd15 pte3/lcd16 pte4/lcd17 pte5/lcd18 pte6/lcd19 lcd22 lcd24 lcd25 v dd lcd26 v ss lcd29 ptb4/miso/sda lcd30 ptb5/mosi/scl lcd31 lcd32 lcd33 ptb2/reset lcd23 vrefo1 ptd5/lcd5 ptd4/lcd4 v ll3 v lcd ptc7/irq/tclk ptc6/acmpo/bkgd/ms ptc5/tpm2ch1 ptc4/tpm2ch0 pte7/lcd20 lcd21 lcd27 lcd28 ptb6/rxd2/spsck ptb7/txd2/ss adp0 ptc0/rxd1 pta6/kbip6/adp10/acmp+ pta7/kbip7/adp11/acmp? v refh v dda ptb0/extal ptb1/xtal ptc3/tpm1ch1 ptc2/tpm1ch 0 v ssa v refl lcd11 ptc1/txd1 lcd34
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 7 9 5 ptd5 lcd5 10 6 ptd4 lcd4 11 7 ptd3 lcd3 12 8 ptd2 lcd2 13 9 ptd1 lcd1 14 10 ptd0 lcd0 15 11 v cap1 16 12 v cap2 17 13 v ll1 18 14 v ll2 19 15 v ll3 20 16 v lcd 21 17 pta6 kbip6 adp10 acmp+ 22 18 pta7 kbip7 adp11 acmp? 23 19 v ssa 24 v refl 25 adp0 26 adp12 27 vrefo1 28 20 v refh 29 v dda 30 21 ptb0 extal 31 22 ptb1 xtal 32 23 v dd 33 24 v ss 34 25 ptb2 reset 26 vrefo2 35 27 ptb4 miso sda 36 28 ptb5 mosi scl 37 29 ptb6 rxd2 spsck 38 30 ptb7 txd2 ss 39 31 ptc0 rxd1 40 32 ptc1 txd1 41 33 ptc2 tpm1ch0 42 34 ptc3 tpm1ch1 43 35 ptc4 tpm2ch0 44 36 ptc5 tpm2ch1 45 37 ptc6 acmpo bkgd ms table 2. pin availability by package pin-count (continued) <-- lowest priority --> highest 80 64 port pin alt 1 alt 2 alt3 alt4
mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 8 46 38 ptc7 irq tclk 47 39 pta0 kbip0 ss adp4 48 40 pta1 kbip1 spsck adp5 49 41 pta2 kbip2 sda miso adp6 50 42 pta3 kbip3 scl mosi adp7 51 43 pta4 kbip4 adp8 lcd43 52 44 pta5 kbip5 adp9 lcd42 53 45 lcd41 54 46 lcd40 55 47 lcd39 56 48 lcd38 57 lcd37 58 lcd36 59 lcd35 60 lcd34 61 lcd33 62 lcd32 63 lcd31 64 49 lcd30 65 50 lcd29 66 51 lcd28 67 52 lcd27 68 53 lcd26 69 54 lcd25 70 55 lcd24 71 56 lcd23 72 57 lcd22 73 58 lcd21 74 59 pte7 lcd20 75 60 pte6 lcd19 76 61 pte5 lcd18 77 62 pte4 lcd17 78 63 pte3 lcd16 79 64 pte2 lcd15 80 1 pte1 lcd14 table 2. pin availability by package pin-count (continued) <-- lowest priority --> highest 80 64 port pin alt 1 alt 2 alt3 alt4
introduction mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 9 3 electrical characteristics 3.1 introduction this section contains electrical and timing specificat ions for the mc9s08ll64 se ries of microcontrollers available at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplem ent are guaranteed by various methods. to give the customer a better understanding, the following classi fication is used and the parameters are tagged accordingly in the tabl es where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond th e limits specified in table 4 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry prot ecting against damage due to high-s tatic voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appr opriate logic volta ge level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 3. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mc9s08ll64 series mcu data sheet, rev. 4 thermal characteristics freescale semiconductor 10 3.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage re gulator circuits, and it is user-determined rather than being controlled by the mcu design. to take p i/o into account in power calc ulations, determine the diff erence between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the diff erence between pin voltage and v ss or v dd will be very small. the average chip-junction temperature (t j ) in c can be obtained from: table 4. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins, except for ptb2 are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma storage temperature range t stg ?55 to 150 c table 5. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 85 c maximum junction temperature t j 95 c thermal resistance single-layer board 80-pin lqfp ja 55 c/w 64-pin lqfp 73 thermal resistance four-layer board 80-pin lqfp ja 42 c/w 64-pin lqfp 54
esd protection and latch-up immunity mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 11 t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglecte d. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the pa rticular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic di scharge (esd) is much less comm on on these devices than on early cmos circuits, normal handling preca utions should be taken to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can with stand exposure to reasonable levels of static without suffer ing any permanent damage. all esd testing is in conformit y with aec-q100 stress test qual ification for automotive grade integrated circuits. during the device qualification, esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametr ic and functional testing is perf ormed per the applicable device specification at room temperature fo llowed by hot temperature, unless in structed otherwise in the device specification. table 6. esd and latch-up test conditions model description symbol value unit human body model series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 charge device model series resistance r1 0 storage capacitance c 200 pf number of pulses per pin ? 3
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 12 3.6 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v table 7. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 2000 ? v 2 charge device model (cdm) v cdm 500 ? v 3 latch-up current at t a = 85 ci lat 100 ? ma table 8. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage 1.8 3.6 v 2 c output high voltage pta[0:3], pta[6:7], ptb[0:7], ptc[0:7] 2 , low-drive strength v oh v dd >1.8 v i load = ?0.6 ma v dd ? 0.5 ? ? v p pta[0:3], pta[6:7], ptb[0:7], ptc[0:7] 2 , high-drive strength v dd > 2.7 v i load = ?10 ma v dd ? 0.5 ? ? c v dd > 1.8 v i load = ?3 ma v dd ? 0.5 ? ? 3 c output high voltage pta[4:5], ptd[0:7], pte[0:7], low-drive strength v oh v dd > 1.8 v i load = ?0.5 ma v dd ? 0.5 ? ? v p pta[4:5], ptd[0:7], pte[0:7], high-drive strength v dd > 2.7 v i load = ?2.5 ma v dd ? 0.5 ? ? c v dd > 1.8 v i load = ?1 ma v dd ? 0.5 ? ? 4d output high current max total i oh for all ports i oht ??100ma 5 c output low voltage pta[0:3], pta[6:7], ptb[0:7], ptc[0:7], low-drive strength v ol v dd >1.8 v i load = 0.6 ma ??0.5 v p pta[0:3], pta[6:7], ptb[0:7], ptc[0:7], high-drive strength v dd > 2.7 v i load = 10 ma ??0.5 c v dd > 1.8 v i load = 3 ma ??0.5 table 6. esd and latch-up test conditions (continued) model description symbol value unit
dc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 13 6 c output low voltage pta[4:5], ptd[0:7], pte[0:7], low-drive strength v ol v dd > 1.8 v i load = 0.5 ma ??0.5 v p pta[4:5], ptd[0:7], pte[0:7], high-drive strength v dd > 2.7 v i load = 3 ma ??0.5 c v dd > 1.8 v i load = 1 ma ??0.5 7d output low current max total i ol for all ports i olt ??100ma 8 p input high voltage all digital inputs v ih v dd > 2.7 v 0.70 v dd ?? v cv dd > 1.8 v 0.85 v dd ?? 9 p input low voltage all digital inputs v il v dd > 2.7 v ? ? 0.35 v dd cv dd > 1.8 v ? ? 0.30 v dd 10 c input hysteresis all digital inputs v hys 0.06 v dd ??mv 11 p input leakage current all input only pins (per pin) |i in |v in = v dd or v ss ?0.025 1 a 12 p hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss ?0.025 1 a 13 p to t a l leakage current 3 total leakage current for all pins |i int |v in = v dd or v ss ?? 3 a 14 p pullup, pulldown resistors all non-lcd pins when enabled r pu, r pd 17.5 ? 52.5 k 15 p pullup, pulldown resistors lcd/gpio pins when enabled r pu, r pd 35 ? 77 k 16 d dc injection current 4, 5, 6 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 17 c input capacitance, all pins c in ?? 8pf 18 c ram retention voltage v ram ?0.61.0v 19 c por re-arm voltage 7 v por 0.9 1.4 2.0 v 20 d por re-arm time t por 10 ? ? s 21 p low-voltage detection threshold v lv d v dd falling v dd rising 1.80 1.88 1.84 1.92 1.88 1.96 v 22 p low-voltage warning threshold v lv w v dd falling v dd rising 2.08 2.14 2.2 v 23 p low-voltage inhibit reset/recover hysteresis v hys ?80?mv 24 p bandgap voltage reference 8 v bg 1.15 1.17 1.18 v table 8. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 14 figure 4. non lcd pins i/o pu llup typical resistor values 1 typical values are measured at 25 c. characterized, not tested. 2 all i/o pins except for lcd pins are in open drain mode. 3 total leakage current is the sum value for all gpio pins. this leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 na. 4 all functional non-supply pins, except for ptb2 are internally clamped to v ss and v dd . 5 input must be current limited to the value sp ecified. to determine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 6 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current greater than maximum injection current. this will be the great est risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 7 por will occur below the minimum voltage. 8 factory trimmed at v dd = 3.0 v, temp = 25 c
dc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 15 figure 5. typical low-side driver (s ink) characteristics (non lcd pins) ? low drive (ptxdsn = 0)
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 16 figure 6. typical low-side driver (sink) characteristics(non lcd pins) ? high drive (ptxdsn = 1)
dc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 17 figure 7. typical high-side (source ) characteristics (non lcd pins) ? low drive (ptxdsn = 0)
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 18 figure 8. typical high-side (source) characteristics(non lcd pins) ? high drive (ptxdsn = 1)
dc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 19 figure 9. typical low-side driver (sink) characteristics (lcd/gpio pins) ? low drive (ptxdsn = 0)
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 20 figure 10. typical low-side driver (sink) characteristics (lcd/gpio pins) ? high drive (ptxdsn = 1)
dc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 21 figure 11. typical high-side (source ) characteristics (lcd/gpio pins) ? low drive (ptxdsn = 0)
mc9s08ll64 series mcu data sheet, rev. 4 dc characteristics freescale semiconductor 22 figure 12. typical high-si de (source) characteristics (lcd/gpio pins) ? high drive (ptxdsn = 1)
supply current characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 23 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 9. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 1 typical values are measured at 25 c. characterized, not tested max unit temp ( c) 1 t run supply current fei mode, all modules on ri dd 20 mhz 3 13.75 17.9 ma ?40 to 85 t 10 mhz 7 ? t 1 mhz 2 ? 2 t run supply current fei mode, all modules off ri dd 20 mhz 3 8.9 ? ma ?40 to 85 t 10 mhz 5.5 ? t 1 mhz 0.9 ? 3 t run supply current lps=0, all modules on ri dd 16 khz fbilp 3 185 ? a ?-40 to 85 t 16 khz fbelp 115 ? 4 t run supply current lps=1, all modules off, running from flash ri dd 16 khz fbelp 3 25 ? a 0 to 70 ? ?40 to 85 t run supply current lps=1, all modules off, running from ram 7.3 ? 0 to 70 ? ?40 to 85 5 t wait mode supply current fei mode, all modules off wi dd 20 mhz 3 4.57 6 ma ?40 to 85 t8 mhz2? t 1 mhz 0.73 ? 6 p stop2 mode supply current s2i dd n/a 3 0.4 1.3 a ?40 to 25 c 46 70 p 8.5 13 85 c 2 0.35 1 ?40 to 25 c 3.9 5 70 c 7.7 10 85 7 p stop3 mode supply current no clocks active s3i dd n/a 3 0.65 1.8 a ?40 to 25 c 5.7 8 70 p 12.2 20 85 c 2 0.6 1.5 ?40 to 25 c 56.8 70 c 11.5 14 85
mc9s08ll64 series mcu data sheet, rev. 4 external oscillator (xoscvlp) characteristics freescale semiconductor 24 figure 13. typical run i dd for fbe and fei, i dd vs. v dd (adc and acmp off, all other modules enabled) 3.8 external oscillator (xoscvlp) characteristics reference figure 14 and figure 15 for crystal or resonator circuits. table 10. stop mode adders num c parameter condition temperature ( c) units ?40257085 1 t lpo 100 100 150 175 na 2 t errefsten range = hgo = 0 750 750 800 850 na 3 t irefsten 1 1 not available in stop2 mode. 63 70 77 81 a 4 t tod does not include clock source current 50 50 75 100 na 5tlvd 1 lvdse = 1 110 110 112 115 a 6tacmp 1 not using the bandgap (bgbe = 0) 12 12 20 23 a 7tadc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) 95 95 101 120 a 8tlcd vireg enabled for contrast control, 1/8 duty cycle, 8x24 configuration for driving 192 segments, 32 hz frame rate, no lcd glass connected. 11613 a
external oscillator (xoscvlp) characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 25 table 11. xoscvlp and ics specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1) high range (range = 1), low power (hgo = 0) f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz 2d load capacitors low range (range=0), low power (hgo=0) other oscillator settings c 1, c 2 see note 2 see note 3 2 load capacitors ( c 1, c 2 ), feedback resistor ( r f ) and series resistor ( r s ) are incorporated internally when range = hgo = 0. 3 see crystal or resonator manufacturer?s recommendation. 3d feedback resistor low range, low power (range=0, hgo=0) 2 low range, high gain (range=0, hgo=1) high range (range=1, hgo=x) r f ? ? ? ? 10 1 ? ? ? m 4d series resistor ? low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? ? 100 0 0 0 0 ? ? ? 0 10 20 k 5c crystal start-up time 4 low range, low power low range, high gain high range, low power high range, high gain 4 proper pc board layout procedures must be followed to achieve specifications. t cstl t csth ? ? ? ? 600 400 5 15 ? ? ? ? ms 6d square wave input clock frequency (erefs = 0, erclken = 1) fee mode fbe or fbelp mode f extal 0.03125 0 ? ? 20 20 mhz mhz
mc9s08ll64 series mcu data sheet, rev. 4 internal clock source (ics) characteristics freescale semiconductor 26 figure 14. typical crystal or resonator circuit: high range and low range/high gain figure 15. typical crystal or resonator circuit: low range/low power 3.9 internal clock source (ics) characteristics table 12. ics frequency specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 max unit 1 c average internal reference frequency ? untrimmed f int_ut 25 32.7 41.66 khz 2 p average internal reference frequency ? user-trimmed f int_t 31.25 ? 39.06 khz 3 p average internal reference frequency ? factory-trimmed f int_t ? 32.7 ? khz 4 t internal reference start-up time t irst ?60100 s 5 p dco output frequency range ? untrimmed low range (dfr = 00) f dco_ut 12.8 16.8 21.33 mhz c mid range (dfr = 01) 25.6 33.6 42.67 6 p dco output frequency range ? trimmed low range (dfr = 00) f dco_t 16 ? 20 mhz p mid range (dfr = 01) 32 ? 40 7c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 8c resolution of trimmed dco output frequency at fixed voltage and temperature (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco xoscvlp extal xtal crystal or resonator r s c 2 r f c 1 xoscvlp extal xtal crystal or resonator
ac characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 27 figure 16. deviation of dco output from trimmed frequency (20 mhz, 3.0 v) 3.10 ac characteristics this section describes timing character istics for each peripheral system. 9c total deviation of trimmed dco output frequency over voltage and temperature f dco_t ? + 0.5 ?1.0 2%f dco 10 c total deviation of trimmed dco output frequency over fixed voltage and temperature range of 0 c to 70 c f dco_t ? 0.5 1%f dco 11 c fll acquisition time 2 t acquire ?? 1ms 12 c long term jitter of dco output clock (averaged over 2 ms interval) 3 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 this specification applies to any time the fll reference sour ce or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (f ei, fee, fbe, fbi). if a cryst al/resonator is being used as the reference, this specification assumes it is already running. 3 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f bus . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. table 12. ics frequency specifications (temperature range = ?40 to 85 c ambient) (continued) num c characteristic symbol min typ 1 max unit
mc9s08ll64 series mcu data sheet, rev. 4 ac characteristics freescale semiconductor 28 3.10.1 control timing figure 17. reset timing table 13. control timing num c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 3.0 v, 25 c unless otherwise stated. max unit 1d bus frequency (t cyc = 1/f bus ) v dd 2.1v v dd > 2.1v f bus dc dc ? ? 10 20 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 s 3d external reset pulse width 2 2 this is the shortest pulse that is guarant eed to be recognized as a reset pin request. t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 t cyc ??ns 5d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ? ? ns 6d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 ? ? s 7d irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronize r is bypassed so shorter pulses can be recognized. t ilih, t ihil 100 1.5 t cyc ? ? ? ? ns 8d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 t cyc ? ? ? ? ns 9c port rise and fall time ? low output drive (ptxds = 0) (load = 50 pf) 5, 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. 6 except for lcd pins in open drain mode. t rise , t fall ? ? 16 23 ? ? ns port rise and fall time ? high output drive (ptxds = 1) (load = 50 pf) 5, 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 5 9 ? ? ns t extrst reset pin
ac characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 29 figure 18. irq /kbipx timing 3.10.2 tpm module timing synchronizer circuits determine the s hortest input pulses that can be re cognized or the fastest clock that can be used as the optional external source to the timer counter. these synchr onizers operate from the current bus rate clock. figure 19. timer external clock figure 20. timer input capture pulse table 14. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t ihil irq /kbipx t ilih irq /kbipx t tclk t clkh t clkl tclk t icpw tpmchn t icpw tpmchn
mc9s08ll64 series mcu data sheet, rev. 4 ac characteristics freescale semiconductor 30 3.10.3 spi timing table 15 and figure 21 through figure 24 describe the timing requir ements for the spi system. table 15. spi timing no. c function symbol min max unit ?d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz d spsck period master slave t spsck 2 4 2048 ? t cyc t cyc d enable lead time master slave t lead 1 / 2 1 ? ? t spsck t cyc d enable lag time master slave t lag 1 / 2 1 ? ? t spsck t cyc d clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns d data setup time (inputs) master slave t su 15 15 ? ? ns ns d data hold time (inputs) master slave t hi 0 25 ? ? ns ns d slave access time t a ?1t cyc d slave miso disable time t dis ?1t cyc d data valid (after spsck edge) master slave t v ? ? 25 25 ns ns d data hold time (outputs) master slave t ho 0 0 ? ? ns ns d rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns d fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns 1 2 3 4 5 6 7 8 9 10 11 12
ac characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 31 figure 21. spi master timing (cpha = 0) figure 22. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) ms bin 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 910 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
mc9s08ll64 series mcu data sheet, rev. 4 ac characteristics freescale semiconductor 32 figure 23. spi slave timing (cpha = 0) figure 24. spi slave timing (cpha = 1) spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1 1. not defined but normally msb of character just received. 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1 1. not defined but normally lsb of character just received 1 2 3 4 ?c 6 7 c 9 10 11 12 4 11 12
analog comparator (acmp) electricals mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 33 3.11 analog comparator (acmp) electricals 3.12 adc characteristics table 16. analog comparator electrical specifications no c characteristic symbol min typical max unit 1 d supply voltage v dd 1.8 ? 3.6 v 2 p supply current (active) i ddac ?2035 a 3 d analog input voltage v ain v ss ? 0.3 ? v dd v 4 p analog input offset voltage v aio ?2040mv 5 c analog comparator hysteresis v h 3.0 9.0 15.0 mv 6 p analog input leakage current i alkg ??1.0 a 7 c analog comparator initialization delay t ainit ??1.0 s table 17. 12-bit adc operating conditions no. characteristic conditions symb min typ 1 1 typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stat ed. typical values are for reference only and are not tested in production. max unit 1 supply voltage absolute v dda 1.8?3.6v delta to v dd (v dd ? v dda ) 2 2 dc potential difference. v dda ?100 0 100 mv 2 ground voltage delta to v ss (v ss ? v ssa ) 2 v ssa ?100 0 100 mv 3 reference voltage high ? v refh 1.8 v dda v dda v 4 reference voltage low ? v refl v ssa v ssa v ssa v 5 input voltage ? v adin v refl ?v refh v 6 input capacitance 8/10/12-bit modes c adin ?4 5pf 7 input resistance ? r adin ?5 7k
mc9s08ll64 series mcu data sheet, rev. 4 adc characteristics freescale semiconductor 34 figure 25. adc input impedance equivalency diagram + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
adc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 35 table 18. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) # characteristic conditions c symb min typ 1 max unit comment 1 supply current adlpc = 1 adhsc = 0 adlsmp = 0 adco = 1 ti dda ?200? a 2 supply current adlpc = 1 adhsc = 1 adlsmp = 0 adco = 1 ti dda ?280? a 3 supply current adlpc = 0 adhsc = 0 adlsmp = 0 adco = 1 ti dda ?370? a 4 supply current adlpc = 0 adhsc = 1 adlsmp = 0 adco = 1 ti dda ?0.61?ma 5 supply current stop, reset, module off i dda ?0.010.8 a 6 adc asynchronous clock source high speed (adlpc = 0) pf adack 23.35 mhz t adack = 1/f adack low power (adlpc = 1) 1.25 2 3.3 7 sample time single/first continuous adlsmp = 0 adhsc = 0 adlsmp = 0 adlsts = xx c ts ? 6 ? adck adhsc = 1 adlsmp = 0 adlsts = xx cts ? 10 ? 8 sample time subsequent continuous adlsmp = 0 adhsc = 0 adlsmp = 0 adlsts = xx c ts ? 4 ? adck adhsc = 1 adlsmp = 0 adlsts = xx cts ? 8 ?
mc9s08ll64 series mcu data sheet, rev. 4 adc characteristics freescale semiconductor 36 9 sample time subsequent continuous or single/first continuous adlsmp = 1 adhsc = 0 adlsmp = 1 adlsts = 00 cts ? 24 ? adhsc = 0 adlsmp = 1 adlsts = 01 cts ? 16 ? adhsc = 0 adlsmp = 1 adlsts = 10 cts ? 10 ? adhsc = 0 adlsmp = 1 adlsts = 11 cts ? 6 ? adhsc = 1 adlsmp = 1 adlsts = 00 cts ? 28 ? adhsc = 1 adlsmp = 1 adlsts = 01 cts ? 20 ? adhsc = 1 adlsmp = 1 adlsts = 10 cts ? 14 ? adhsc = 1 adlsmp = 1 adlsts = 11 cts ? 10 ? 10 to t a l unadjusted error 12-bit mode 3.6 > v dda > 2.7v t e tue ? ?2.5 to 3.25 4 lsb 2 includes quantization 12-bit mode, 2.7 > v dda > 1.8v t 3.25 ?5.5 to 6.5 10-bit mode t ? 1 2.5 8-bit mode t ? 0.5 1.0 11 differential non-linearity 12-bit mode t dnl ? ?1 to 1.75 ?1.5 to 2.5 lsb 2 10-bit mode 3 t? 0.5 1.0 8-bit mode 3 t? 0.3 0.5 table 18. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) # characteristic conditions c symb min typ 1 max unit comment
adc characteristics mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 37 12 integral non-linearity 12-bit mode t inl ? ?1.5 to 2.25 2.75 lsb 2 10-bit mode t ? 0.5 1.0 8-bit mode t ? 0.3 0.5 13 zero-scale error 12-bit mode t e zs ? 1 ?1.25 to 1 lsb 2 v adin = v ssa 10-bit mode t ? 0.5 1 8-bit mode t ? 0.5 0.5 14 full-scale error 12-bit mode t e fs ? 1.0 ?3.5 to 2.25 lsb 2 v adin = v dda 10-bit mode t ? 0.5 1 8-bit mode t ? 0.5 0.5 15 quantization error 12-bit mode de q ? ?1 to 0 ? lsb 2 10-bit mode ? ? 0.5 8-bit mode ? ? 0.5 16 input leakage error 12-bit mode de il ? 2? lsb 2 pad leakage 4 * r as 10-bit mode ? 0.2 4 8-bit mode ? 0.1 1.2 17 temp sensor slope ?40 c? 25 c dm ? 1.646 ? mv/ c 25 c? 125 c ? 1.769 ? 18 temp sensor voltage 25 cdv temp25 ? 701.2 ? mv 1 typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh ? v refl )/2 n 3 monotonicity and no-missing-codes guar anteed in 10-bit and 8-bit modes. 4 based on input pad leakage current. refer to pad electricals. table 18. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) # characteristic conditions c symb min typ 1 max unit comment
mc9s08ll64 series mcu data sheet, rev. 4 vref specifications freescale semiconductor 38 3.13 vref specifications table 19. vref electrical specifications num characteristic sym bol typical min max unit 1 supply voltage v dd ? 1.80 3.60 v 2 operating temperature range t op ? ?40 105 c 3 maximum load ? ? ? 10 ma operation across temperature 4 v room temp v room temp 1.15 ? ? v 5 untrimmed ?40 c untrimmed ?40 c ? ?2 to ?6 from room temp voltage mv 6 trimmed ?40 c trimmed ?40 c ? 1 from room temp voltage mv 7 untrimmed 0 c untrimmed 0 c ? +1 to ?2 from room temp voltage mv trimmed 0 c trimmed 0 c ? 0.5 from room temp voltage mv 8 untrimmed 50 c untrimmed 50 c ? +1 to ?2 from room temp voltage mv 9 trimmed 50 c trimmed 50 c ? 0.5 from room temp voltage mv 10 untrimmed 85 c untrimmed 85 c ? 0 to ?4 from room temp voltage mv 11 trimmed 85 c trimmed 85 c ? 0.5 from room temp voltage mv 12 untrimmed 125 c untrimmed 125 c ? ?2 to ?6 from room temp voltage mv 13 trimmed 125 c trimmed 125 c ? 1 from room temp voltage mv 14 load bandwidth ? ? ? ? ? 15 load regulation mode = 10 at 1ma load mode = 10 ? 20 100 v/ma 16 line regulation (power supply rejection) dc ? 0.1 from room temp voltage mv ac ? ?60 db power consumption 17 powered down current (stop mode, vrefen = 0, vrsten = 0) i ? ? .100 a 18 bandgap only (mode[1:0] 00) i ? ? 75 a 19 low-power buffer (mode[1:0] 01) i ? ? 125 a 20 tight-regulation buffer (mode[1:0] 10) i ? ? 1.1 ma 21 reserved (mode[1:0] 11) ? ? ? ? ?
lcd specifications mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 39 3.14 lcd specifications 3.15 flash specifications this section provides details about program/erase times and program-erase endurance for the flash memory. program and erase operations do not require any special power s ources other than the normal v dd supply. for more detailed information about progra m/erase operations, see the memory section. table 20. lcd electricals, 3-v glass no. c characteristic symbol min typ max unit 1 d lcd supply voltage v lcd .9 1.5 1.8 v 2 d lcd frame frequency f frame 28 30 58 hz 3 d lcd charge pump capacitance c lcd ?100100 nf 4 d lcd bypass capacitance c bylcd ?100100 nf 5 d lcd glass capacitance c glass ? 2000 8000 pf 6 dv ireg hrefsel = 0 v ireg .89 1.00 1.15 v 7 hrefsel = 1 1.49 1.67 1.85 1 1 v ireg max can not exceed v dd ?.15 v 8dv ireg trim resolution rtrim 1.5 ? ? % v ireg 9 dv ireg ripple hrefsel = 0 ? ? ? .1 v 10 hrefsel = 1 ? ? ? .15 11 d v lcd buffered adder 2 2 vsupply = 10, bypass = 0 i buff ?1 a table 21. flash characteristics no. c characteristic symbol min typical max unit 1d supply voltage for program/erase ?40 c to 85 c v prog/erase 1.8 ? 3.6 v 2 d supply voltage for read operation v read 1.8 ? 3.6 v 3 d internal fclk frequency 1 f fclk 150 ? 200 khz 4 d internal fclk period (1/fclk) t fcyc 5 ? 6.67 s 5 p byte program time (random location) 2 t prog 9t fcyc 6 p byte program time (burst mode) 2 t burst 4t fcyc 7 p page erase time 2 t page 4000 t fcyc 8 p mass erase time 2 t mass 20,000 t fcyc 9 d byte program current 3 r iddbp ?4?ma
mc9s08ll64 series mcu data sheet, rev. 4 emc performance freescale semiconductor 40 3.16 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and char acteristics of external components as well as mcu software operation all pl ay a significant role in emc performance. the system designer should consult freescale a pplications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance specifi cally targeted at optimizing emc performance. 3.16.1 radiated emissions microcontroller radiated rf emis sions are measured from 150 khz to 1 ghz using th e tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installe d on a custom emc evalua tion board while running specialized emc test software. the radiated emissions fr om the microcontroller are measured in a tem cell in two package orientations (north and east). 4 ordering information this appendix contains orderi ng information for the device numbering system mc9s08ll64 and MC9S08LL36 devices. see table 1 for feature summary by package information. 10 d page erase current 3 r iddpe ?6?ma 11 c program/erase endurance 4 t l to t h = ?40 c to 85 c t = 25 c ? 10,000 ? 100,000 ? ? cycles 12 c data retention 5 t d_ret 15 100 ? years 1 the frequency of this clock is controlled by a software setting. 2 these values are hardware state machine controlled. user code does not need to count cycles. this information supplied for calculating approximate time to program and erase. 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. 4 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 5 typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on ho w freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. table 22. device numbering system device number 1 memory available packages 2 flash ram mc9s08ll64 64 kb 4000 80 lqfp 64 kb 4000 64 lqfp MC9S08LL36 36 kb 4000 64 lqfp table 21. flash characteristics (continued) no. c characteristic symbol min typical max unit
device numbering system mc9s08ll64 series mcu data sheet, rev. 4 freescale semiconductor 41 4.1 device numbering system example of the device numbering system: 4.2 package information 4.3 mechanical drawings table 23 provides the available package types and their document numbers. the latest package outline/mechanical drawings are available on th e mc9s08ll64 series product summary pages at http://www.freescale.com . to view the latest drawing, either: ? click on the appropriate link in table 23, or ? open a browser to the freescale ? website ( http://www.freescale.com ), and enter the appropriate document number (from table 23 ) in the ?enter keyword? search box at the top of the page. 1 see ta b l e 1 for a complete description of modules included on each device. 2 see ta b l e 2 3 for package information. table 23. package descriptions pin count package type abbreviation designator case no. document no. 80 low quad flat package lqfp lk 917a 98ass23237w 64 low quad flat package lqfp lh 840f 98ass23234w mc temperature range family memory status core (c = ?40 c to 85 c) (9 = flash-based) 9 s08 (mc = fully qualified) package designator (see ta b l e 2 3 ) approximate flash size in kb ll 64 c xx

mc9s08ll64 rev. 4, 08/2009 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunde r to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental dam ages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable atto rney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved.

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